Constraining Operation Delay for Dynamic Power Optimization of Asynchronous Circuits

In this paper, we propose a dynamic power optimization method for asynchronous circuits with bundled-data implementation constraining operation delay. In asynchronous circuits, we can change the execution time of each operation freely under a given latency constraint. Therefore, the proposed method relaxes the execution time of operations which consume more power while it tightens the execution time of operations which consume less power. In the experiments, we evaluate the effects of the proposed method by comparing area, execution time, power consumption, and energy consumption among synchronous circuits, asynchronous circuits without the proposed method, and asynchronous circuits with the proposed method. As a result, we can reduce dynamic power and energy consumption about 11% and 14% on average.